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ADVANCE INFORMATION
80C196EA/83C196EA CHMOS 16-BIT MICROCONTROLLER
Automotive
s 40 MHz operation s Optional clock doubler s 2 Mbytes of linear address space s 1 Kbyte of register RAM s 3 Kbytes of code RAM s 8 Kbytes of ROM s Register-to-register architecture s Stack overflow/underflow monitor with user-defined upper and lower stack pointer boundary limits s 2 peripheral interrupt handlers (PIH) provide direct hardware handling of up to 16 peripheral interrupts s Peripheral transaction server (PTS) with high-speed, microcoded interrupt service routines s Up to 83 I/O port pins s 2 full-duplex serial ports with dedicated baud-rate generators s Enhanced synchronous serial unit s 8 pulse-width modulator (PWM) outputs with 8-bit resolution s 16-bit watchdog timer s Sixteen 10-bit A/D channels with autoscan mode and dedicated results registers s Serial debug unit provides read and write access to code RAM with no CPU overhead s Chip-select unit (CSU) s 3 chip-select pins s Dynamic demultiplexed/multiplexed address/data bus for each chip-select s Programmable wait states (0, 1, 2, or 3) for each chip-select s Programmable bus width (8- or 16-bit) for each chip-select s Programmable address range for each chip-select s Event processor array (EPA) s 4 flexible 16-bit timer/counters s 17 high-speed capture/compare channels s 8 output-only channels capture value of any other timer upon compare, providing easy conversion between angle and time domains s Programmable clock output signal s 160-pin QFP package s Complete system development support s High-speed CHMOS technology
The 8xC196EA is the first member of a new family of microcontrollers with features that are useful in automotive applications, such as powertrain control. Two Mbytes of linear address space provide more space for high-level language compilation. A demultiplexed address/data bus and three chip-select signals make it easier to design low-cost memory solutions. The external bus can dynamically switch between multiplexed and demultiplexed operation. NOTE This datasheet contains information on products being sampled or in the initial production phase of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
COPYRIGHT (c) INTEL CORPORATION, 1997
August 1997
Order Number: 272788-003
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. *Third-party brands and names are the property of their respective owners. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-548-4725
CONTENTS
80C196EA/83C196EA CHMOS 16-bit Microcontroller 1.0 Product Overview ................................................................................................................ 1 2.0 Nomenclature Overview ...................................................................................................... 2 3.0 Pinout .................................................................................................................................. 3 4.0 Signals ................................................................................................................................ 7 5.0 Address Map ..................................................................................................................... 15 6.0 Electrical Characteristics ................................................................................................... 17 6.1 DC Characteristics........................................................................................................ 17 6.2 AC Characteristics -- Multiplexed Bus Mode............................................................... 19 6.3 AC Characteristics -- Demultiplexed Bus Mode .......................................................... 23 6.4 Deferred Bus Timing Mode........................................................................................... 27 6.5 AC Characteristics -- Serial Port, Shift Register Mode................................................ 28 6.6 AC Characteristics -- Synchronous Serial Port ........................................................... 29 6.7 A/D Sample and Conversion Times ............................................................................. 30 6.7.1 AC Characteristics -- A/D Converter, 10-bit Mode ...............................................31 6.7.2 AC Characteristics -- A/D Converter, 8-bit Mode .................................................32 6.8 External Clock Drive ..................................................................................................... 34 6.9 Test Output Waveforms ............................................................................................... 35 7.0 Thermal Characteristics .................................................................................................... 36 7.1 8xC196EA Errata ......................................................................................................... 36 8.0 DataSheet Revision History .............................................................................................. 37
ADVANCE INFORMATION
iii
CONTENTS
FIGURES
Figure Page 1. 8xC196EA Block Diagram.................................................................................................... 1 2. Product Nomenclature ......................................................................................................... 2 3. 8xC196EA 160-pin QFP Package........................................................................................ 3 4. System Bus Timing Diagram (Multiplexed Bus Mode) .......................................................21 5. READY Timing Diagram (Multiplexed Bus Mode)..............................................................22 6. System Bus Timing Diagram (Demultiplexed Bus Mode) ..................................................25 7. READY Timing Diagram (Demultiplexed Bus Mode) .........................................................26 8. Deferred Bus Mode Timing Diagram..................................................................................27 9. Serial Port Waveform -- Shift Register Mode ....................................................................28 10. Synchronous Serial Port ....................................................................................................29 11. External Clock Drive Waveforms........................................................................................34 12. AC Testing Output Waveforms...........................................................................................35 13. Float Waveforms During 5.0 Volt Testing...........................................................................35
iv
ADVANCE INFORMATION
CONTENTS
TABLES
Table Page 1. Description of Product Nomenclature................................................................................... 2 2. 8xC196EA 160-pin QFP Package Pin Assignments ............................................................4 3. Pin Assignment Arranged by Functional Categories............................................................5 4. Signal Descriptions .............................................................................................................. 7 5. 8xC196EA Address Map ....................................................................................................15 6. DC Characteristics at VCC = 4.5 V - 5.5 V .........................................................................17 7. AC Characteristics, Multiplexed Bus Mode ........................................................................19 8. AC Timing Symbol Definitions............................................................................................20 9. AC Characteristics, Demultiplexed Bus Mode....................................................................23 10. Serial Port Timing -- Shift Register Mode..........................................................................28 11. Synchronous Serial Port Timing.........................................................................................29 12. 10-bit A/D Operating Conditions (1) ...................................................................................31 13. 10-bit Mode A/D Characteristics Over Specified Operating Conditions (7)........................31 14. 8-bit A/D Operating Conditions (1) .....................................................................................32 15. 8-bit Mode A/D Characteristics Over Specified Operating Conditions (7)..........................33 16. External Clock Drive...........................................................................................................34 17. Thermal Characteristics .....................................................................................................36 18. Revision History (rev. 002 - 003)........................................................................................37 19. Revision History (rev. 001 - 002)........................................................................................39 20. Revision History (rev. 001) .................................................................................................40
ADVANCE INFORMATION
v
8xC196EA -- AUTOMOTIVE
1.0
PRODUCT OVERVIEW
Port 11
Port 10
EPORT
Port 12
Watchdog Timer
Stack Overflow Module
A/D Converter
Pulse-width Modulators
SSIO0 SSIO1
Peripheral Addr Bus (10)
Peripheral Data Bus (16)
SIO0
Baud-rate Generator
Bus Control A20:16 A15:0 AD15:0
Memory Data Bus (16)
Memory Addr Bus (24)
Bus Controller
Chip-select Unit
Port 2
Peripheral Interrupt Handler Peripheral Transaction Server Interrupt Controller
SIO1
Baud-rate Generator
Bus-Control Interface Unit Queue Microcode Engine
Ports 7,8
17 Capture/ Compares EPA 4 Timers 8 Output/ Simulcaptures
Source (16) Port 9 Memory Interface Unit
ALU
Register RAM 1 Kbyte
Destination (16)
Code/Data RAM 3 Kbytes
Serial Debug Unit
ROM 8 Kbytes A3178-03
Figure 1. 8xC196EA Block Diagram The 8xC196EA is highly integrated with an enhanced peripheral set. The serial debug unit (SDU) provides system debug and development capabilities. The SDU can set a single hardware breakpoint and provides read and write access to code RAM through a high-speed, dedicated serial link. A stack overflow/underflow monitor assists in code development by causing an unmaskable interrupt if the stack pointer crosses a user-defined boundary. The 16-channel A/D converter supports an auto-scan mode that operates with no
ADVANCE INFORMATION
1
8xC196EA -- AUTOMOTIVE
CPU overhead. Each A/D channel has a dedicated result register. The EPA supports high-speed input captures and output compares with 17 programmable, high-speed capture/compare channels. Eight output-only channels provide support for time-base conversions by capturing the value of one of four timers when a compare occurs.
2.0
NOMENCLATURE OVERVIEW
X
m Te
XX
Pa ck
8
X
o Pr
X
o Pr
XXXXX
o Pr
XX
De vic
gr
ce
du
Table 1. Description of Product Nomenclature Parameter Temperature and Burn-in Options Packaging Options Program Memory Options Process Information Product Family Device Speed Options A S 3 0 C 196EA no mark 40 MHz Description Automotive operating temperature range (-40 C to 125 C case) with Intel standard burn-in. QFP Internal ROM CPU only - no internal ROM CHMOS
pe tu ra
Figure 2. Product Nomenclature
ag ing Op tio ns
am
pe eS
ss o Inf
ct Fa
Me
a re nd
mi
ed
mo
rm ati on
ly
ry
Bu -in rn
Op n tio
s
Op tio ns
A2815-01
2
ADVANCE INFORMATION
8xC196EA -- AUTOMOTIVE
3.0
PINOUT
A15 A14 A13 A12 A11 A10 A9 A8 VCC VSS A7 A6 A5 A4 A3 A2 A1 A0 P9.7 / OS7 P9.6 / OS6 P9.5 / OS5 P9.4 / OS4 P9.3 / OS3 P9.2 / OS2 P9.1 / OS1 P9.0 / OS0 P7.0 / EPA0 / T1CLK P7.1 / EPA1 / T1RST P7.2 / EPA2 / T2CLK P7.3 / EPA3 / T2RST P7.4 / EPA4 / T3CLK P7.5 / EPA5 / T3RST VSS VCC P7.6 / EPA6 / T4CLK P7.7 / EPA7 / T4RST P8.7 / EPA15 P8.6 / EPA14 P8.5 / EPA13 NC
AD0 / P3.0 AD1 / P3.1 AD2 / P3.2 AD3 / P3.3 AD4 / P3.4 AD5 / P3.5 AD6 / P3.6 AD7 / P3.7 VCC VCC VSS VSS AD8 / P4.0 AD9 / P4.1 AD10 / P4.2 AD11 / P4.3 AD12 / P4.4 AD13 / P4.5 AD14 / P4.6 AD15 / P4.7 P5.7 / RPD P5.4/BREQ#/TMODE# P5.6 / READY P5.1 / INST P5.0 / ALE P5.5 / BHE# / WRH# P5.3 / RD# P5.2 / WR# / WRL# VSS VCC A20 / EPORT.4 A16 / EPORT.0 A17 / EPORT.1 A18 / EPORT.2 A19 / EPORT.3 EPORT.5 / CS0# EPORT.6 / CS1# EPORT.7 / CS2# NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
AS8xC196EA
View of component as mounted on PC board
P8.4 / EPA12 P8.3 / EPA11 P8.2 / EPA10 P8.1 / EPA9 P8.0 / EPA8 P10.5 P10.4 / EPA16 P10.3 / SD1 P10.2 / SC1 / CHS# P10.1 / SD0 P10.0 / SC0 P11.4 / PWM4 P11.5 / PWM5 P11.6 / PWM6 P11.7 / PWM7 P11.3 / PWM3 P11.2 / PWM2 P11.1 / PWM1 P11.0 / PWM0 VSS VCC P12.4 P12.0 P12.1 P12.2 P12.3 VSS NC VCC NC RESET# NMI VREF ANGND ACH0 ACH1 ACH2 ACH3 ACH4 ACH5
This pin supplies voltage to the phase-locked loop circuitry, so use extra care to keep it stable. This pin supplies voltage to the code RAM. Maintain at 5 volts to retain data in code RAM. NC pins must be unconnected to prevent accidental entry into a test mode.
A4461-01
ADVANCE INFORMATION
NC NC NC NC EA# VCC PLLEN XTAL2 XTAL1 VSS VCC P2.7 / CLKOUT P2.6 / ONCE# P2.5 P2.4 /RXD1 P2.3 / TXD1 P2.2 / EXTINT P2.1 / RXD0 P2.0 / TXD0 VCC VSS CRBUSY# CROUT CRIN CRDCLK VCC NC VSS VSS ACH15 ACH14 ACH13 ACH12 ACH11 ACH10 ACH9 ACH8 ACH7 ACH6 NC
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Figure 3. 8xC196EA 160-pin QFP Package
3
8xC196EA -- AUTOMOTIVE
Table 2. 8xC196EA 160-pin QFP Package Pin Assignments (Sheet 1 of 2) Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Name AD0 / P3.0 AD1 / P3.1 AD2 / P3.2 AD3 / P3.3 AD4 / P3.4 AD5 / P3.5 AD6 / P3.6 AD7 / P3.7 V CC V CC V SS V SS AD8 / P4.0 AD9 / P4.1 AD10 / P4.2 AD11 / P4.3 AD12 / P4.4 AD13 / P4.5 AD14 / P4.6 AD15 / P4.7 P5.7 / RPD P5.4/BREQ#/TMODE# P5.6 / READY P5.1 / INST P5.0 / ALE P5.5 / BHE# / WRH# P5.3 / RD# P5.2 / WR# / WRL#
Pin
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
Name NC NC NC NC EA# VCC PLLEN XTAL2 XTAL1 VSS VCC P2.7 / CLKOUT P2.6 / ONCE# P2.5 P2.4 / RXD1 P2.3 / TXD1 P2.2 / EXTINT P2.1 / RXD0 P2.0 / TXD0 VCC VSS CRBUSY# CROUT CRIN CRDCLK VCC NC VSS
Pin
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
Name ACH5 ACH4 ACH3 ACH2 ACH1 ACH0 ANGND VREF NMI RESET# NC VCC NC VSS P12.3 P12.2 P12.1 P12.0 P12.4 VCC VSS P11.0 / PWM0 P11.1 / PWM1 P11.2 / PWM2 P11.3 / PWM3 P11.7 / PWM7 P11.6 / PWM6 P11.5 / PWM5
Pin
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148
Name NC P8.5 / EPA13 P8.6 / EPA14 P8.7 / EPA15 P7.7 / EPA7 / T4RST P7.6 / EPA6 / T4CLK VCC VSS P7.5 / EPA5 / T3RST P7.4 / EPA4 / T3CLK P7.3 / EPA3 / T2RST P7.2 / EPA2 / T2CLK P7.1 / EPA1 / T1RST P7.0 / EPA0 / T1CLK P9.0 / OS0 P9.1 / OS1 P9.2 / OS2 P9.3 / OS3 P9.4 / OS4 P9.5 / OS5 P9.6 / OS6 P9.7 / OS7 A0 A1 A2 A3 A4 A5
4
ADVANCE INFORMATION
8xC196EA -- AUTOMOTIVE
Table 2. 8xC196EA 160-pin QFP Package Pin Assignments (Sheet 2 of 2) Pin
29 30 31 32 33 34 35 36 37 38 39 40
Name VSS VCC A20 / EPORT.4 A16 / EPORT.0 A17 / EPORT.1 A18 / EPORT.2 A19 / EPORT.3 EPORT.5 / CS0# EPORT.6 / CS1# EPORT.7 / CS2# NC NC
Pin
69 70 71 72 73 74 75 76 77 78 79 80
Name V SS ACH15 ACH14 ACH13 ACH12 ACH11 ACH10 ACH9 ACH8 ACH7 ACH6 NC
Pin
109 110 111 112 113 114 115 116 117 118 119 120
Name P11.4 / PWM4 P10.0 / SC0 P10.1 / SD0 P10.2 / SC1 P10.3 / SD1 P10.4 / EPA16 P10.5 P8.0 / EPA8 P8.1 / EPA9 P8.2 / EPA10 P8.3 / EPA11 P8.4 /EPA12
Pin
149 150 151 152 153 154 155 156 157 158 159 160
Name A6 A7 VSS VCC A8 A9 A10 A11 A12 A13 A14 A15
Table 3. Pin Assignment Arranged by Functional Categories (Sheet 1 of 2) Addr & Data Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 Pin 143 144 145 146 147 148 149 150 153 154 155 156 157 158 159 160 32 33 34 35 31 Input/Output Name P2.0 / TXD0 P2.1 / RXD0 P2.2 P2.3 / TXD1 P2.4 / RXD1 P2.5 P2.6 P2.7 P3.0 P3.1 R3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 Pin 59 58 57 56 55 54 53 52 1 2 3 4 5 6 7 8 13 14 15 16 17 Input/Output (Cont'd) Name EPORT.7 P7.0 / EPA0 / T1CLK P7.1 / EPA1 / T1RST P7.2 / EPA2 / T2CLK P7.3 / EPA3 / T2RST P7.4 / EPA4 / T3CLK P7.5 / EPA5 / T3RST P7.6 / EPA6 / T4CLK P7.7 / EPA7 / T4RST P8.0 / EPA8 P8.1 / EPA9 P8.2 / EPA10 P8.3 / EPA11 P8.4 / EPA12 P8.5 / EPA13 P8.6 / EPA14 P8.7 / EPA15 P9.0 / OS0 P9.1 / OS1 P9.2 / OS2 P9.3 / OS3 Pin 38 134 133 132 131 130 129 126 125 116 117 118 119 120 122 123 124 135 136 137 138 ACH0 ACH1 ACH2 ACH3 ACH4 ACH5 ACH6 ACH7 ACH8 ACH9 ACH10 ACH11 ACH12 Analog Inputs Name Pin 86 85 84 83 82 81 79 78 77 76 75 74 73 P12.0 P12.1 P12.2 P12.3 P12.4 Input/Output (Cont'd) Name Pin 98 97 96 95 99
ADVANCE INFORMATION
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8xC196EA -- AUTOMOTIVE
Table 3. Pin Assignment Arranged by Functional Categories (Sheet 2 of 2) AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 1 2 3 4 5 6 7 8 13 14 15 16 17 18 19 20 P4.5 P4.6 P4.7 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 EPORT.0 EPORT.1 EPORT.2 EPORT.3 EPORT.4 EPORT.5 EPORT.6 Name ANGND VCC VSS VREF 87 9, 10, 30, 46, 51, 60, 66, 92, 100, 127, 152 11, 12, 29, 50, 61, 68, 69, 94, 101, 128, 151 88 No Connection Name NC Pins 39-44, 67, 69, 80, 91, 93, 121 18 19 20 25 24 28 27 22 26 23 21 32 33 34 35 31 36 37 P9.4 / OS4 P9.5 / OS5 P9.6 / OS6 P9.7 / OS7 P10.0 / SC0 P10.1 / SD0 P10.2 / SC1 P10.3 / SD1 P10.4 / EPA16 P10.5 P11.0 / PWM0 P11.1 / PWM1 P11.2 / PWM2 P11.3 / PWM3 P11.4 / PWM4 P11.5 / PWM5 P11.6 / PWM6 P11.7 / PWM7 Pins EA# EXTINT NMI ONCE# PLLEN RESET# RPD TMODE# XTAL1 XTAL2

139 140 141 142 110 111 112 113 114 115 102 103 104 105 109 108 107 106
ACH13 ACH14 ACH15
72 71 70
Bus Control & Status Name ALE BHE#/WRH# BREQ# CS0# CS1# CS2# INST RD# READY Pin 25 26 22 36 37 38 24 27 23
WR#/WRL# Name CLKOUT
28 Pin 52 45 57 89 53 47 90 21 22 49 48
Power & Ground
Processor Control
This pin supplies voltage to the phase-locked loop circuitry, so use extra care to keep it stable. This pin supplies voltage to code RAM. To retain data, maintain 5 volts. Always leave NC (no connect) pins unconnected to prevent accidental entry into test modes.
Code Debug Name CRBUSY# CRDCLK CRIN CROUT Pin 62 65 64 63
6
ADVANCE INFORMATION
8xC196EA -- AUTOMOTIVE
4.0
SIGNALS
Table 4. Signal Descriptions (Sheet 1 of 8) Name Type O Description System Address Bus These address lines provide address bits 0-15 during the entire external memory cycle during both multiplexed and demultiplexed bus modes. Address Lines 16-20 These address lines provide address bits 16-20 during the entire external memory cycle, supporting extended addressing of the 2 Mbyte address space. NOTE: Internally, there are 24 address bits; however, only 21 external address pins (A20:0) are implemented. The internal address space is 16 Mbytes (000000 FFFFFFH) and the external address space is 2 Mbytes (00000 1FFFFFH). The device resets to FF2080H in internal memory or 1F2080H in external memory. A20:16 are multiplexed with EPORT.4:0. Analog Channels These pins are analog inputs to the A/D converter. The ANGND and VREF pins must be connected for the A/D converter to function. Address/Data Lines The function of these pins depend on the bus size and mode. When a bus access is not occurring, these pins revert to their I/O port function. 16-bit Multiplexed Bus Mode: AD15:0 drive address bits 0-15 during the first half of the bus cycle and drive or receive data during the second half of the bus cycle. 8-bit Multiplexed Bus Mode: AD15:8 drive address bits 8-15 during the entire bus cycle. AD7:0 drive address bits 0-7 during the first half of the bus cycle and drive or receive data during the second half of the bus cycle. 16-bit Demultiplexed Mode: AD15:0 drive or receive data during the entire bus cycle. 8-bit Demultiplexed Mode: AD7:0 drive or receive data during the entire bus cycle. AD15:8 drive the data that is currently on the high byte of the internal bus. AD7:0 share package pins P3.7:0. AD15:8 share package pins P4.7:0. Address Latch Enable This active-high output signal is asserted only during external memory cycles. ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus (A20:16 and AD15:0 for a multiplexed bus; A20:0 for a demultiplexed bus). An external latch can use this signal to demultiplex address bits 0-15 from the address/data bus in multiplexed mode. ALE shares a package pin with P5.0. Analog Ground ANGND must be connected for A/D converter operation. ANGND and VSS should be nominally at the same potential.
A15:0
A20:16
I/O
ACH15:0
I
AD15:0
I/O
ALE
O
ANGND
GND
ADVANCE INFORMATION
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8xC196EA -- AUTOMOTIVE
Table 4. Signal Descriptions (Sheet 2 of 8) Name BHE# Type O Description Byte High Enable During 16-bit bus cycles, this active-low output signal is asserted for word and high-byte reads and writes to external memory. BHE# indicates that valid data is being transferred over the upper half of the system data bus. Use BHE#, in conjunction with AD0, to determine which memory byte is being transferred over the system bus: BHE# 0 0 1
AD0 0 1 0
Byte(s) Accessed both bytes high byte only low byte only
BHE# shares a package pin with P5.5 and WRH#. The chip configuration register 0 (CCR0) determines whether this pin functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
BREQ#
O
Bus Request This active-low output signal is asserted during a hold cycle when the bus controller has a pending external memory cycle. You must enable the bus-hold protocol before using this signal. BREQ# shares a package pin with P5.4. Clock Output Output of the internal clock generator. The CLKOUT frequency can be programmed to one of five frequencies: the internal operating frequency (f) divided by a factor of two, four, eight, or sixteen, or the same frequency as the oscillator input (FXTAL1). CLKOUT has a 50% duty cycle. CLKOUT shares a package pin with P2.7 Code RAM Busy This signal indicates that the serial debug unit (SDU) is not ready to conduct a transaction. Code RAM Clock Provides the clock signal for the serial debug unit (SDU). The maximum clock frequency equals the operating frequency (f) divided by two. Code RAM Data Input Serial input for test instructions and data into the serial debug unit (SDU). Data is transferred in 8-bit bytes with the most-significant bit (MSB) first. Each bit is sampled on the rising edge of CRDCLK. Code RAM Data Output Serial output for data from the serial debug unit (SDU). Data is transferred in 8-bit bytes with the most-significant bit (MSB) first. Each bit is valid on the rising edge of CRDCLK.
CLKOUT
O
CRBUSY#
O
CRDCLK
I
CRIN
I
CROUT
O
8
ADVANCE INFORMATION
8xC196EA -- AUTOMOTIVE
Table 4. Signal Descriptions (Sheet 3 of 8) Name CS2:0# Type O Description Chip-select Lines 0-2 The active-low output CSx# is asserted during an external memory cycle when the address to be accessed is in the range programmed for chip select x. If the external memory address is outside the range assigned to the three chip selects, no chip-select output is asserted and the bus configuration defaults to the CS2# values. Immediately following reset, CS0# is automatically assigned to the range FF2000 FF20FFH (1F2000 1F20FFH if external). CS2:0# share package pins with EPORT.7:5. External Access This input determines whether memory accesses to special-purpose and program memory partitions (FF2000 FF3FFFH) are directed to internal or external memory. These accesses are directed to internal memory if EA# is held high and to external memory if EA# is held low. For an access to any other memory location, the value of EA# is irrelevant. EA# is sampled and latched only on the rising edge of RESET#. Changing the level of EA# after reset has no effect. On devices with no internal nonvolatile memory, always connect EA# to VSS. Event Processor Array (EPA) Capture/Compare Channels High-speed input/output signals for the EPA capture/compare channels. EPA16:0 share package pins with the following signals: EPA0/P7.0/T1CLK, EPA1/P7.1/T1RST, EPA2/P7.2/T2CLK, EPA3/P7.3/T2RST, EPA4/P7.4/T3CLK, EPA5/P7.5/T3RST, EPA6/P7.6/T4CLK, EPA7/P7.7/T4RST, EPA8/P8.0, EPA9/P8.1, EPA10/P8.2, EPA11/P8.3, EPA12/P8.4, EPA13/P8.5, EPA14/P8.6, EPA15/P8.7, and EPA16/P10.4. Extended Addressing Port This is a standard 8-bit, bidirectional port. EPORT.4:0 share package pins with A20:16. EPORT7:5 share package pins with CS2:0#. EXTINT I External Interrupt In normal operating mode, a rising edge on EXTINT sets the EXTINT interrupt pending bit. EXTINT is sampled during phase 2 (CLKOUT high). The minimum high time is one state time. In powerdown mode, asserting the EXTINT signal for at least 50 ns causes the device to resume normal operation. The interrupt need not be enabled, but the pin must be configured as a special-function input. If the EXTINT interrupt is enabled, the CPU executes the interrupt service routine. Otherwise, the CPU executes the instruction that immediately follows the command that invoked the power-saving mode. In idle mode, asserting any enabled interrupt causes the device to resume normal operation. EXTINT shares a package pin with P2.2.
EA#
I
EPA16:0
I/O
EPORT.7:0
I/O
ADVANCE INFORMATION
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8xC196EA -- AUTOMOTIVE
Table 4. Signal Descriptions (Sheet 4 of 8) Name INST Type O Description Instruction Fetch This active-high output signal is valid only during external memory bus cycles. When high, INST indicates that an instruction is being fetched from external memory. The signal remains high during the entire bus cycle of an external instruction fetch. INST is low for data accesses, including interrupt vector fetches and chip configuration byte reads. INST is low during internal memory fetches. INST shares a package pin with P5.1. Nonmaskable Interrupt In normal operating mode, a rising edge on NMI generates a nonmaskable interrupt. NMI has the highest priority of all prioritized interrupts. Assert NMI for greater than one state time to guarantee that it is recognized. On-circuit Emulation Holding ONCE# low during the rising edge of RESET# places the device into on-circuit emulation (ONCE) mode. PLLEN must also be held low. This mode puts all pins into a high-impedance state, thereby isolating the device from other components in the system. The value of ONCE# is latched when the RESET# pin goes inactive. While the device is in ONCE mode, you can debug the system using a clip-on emulator. To exit ONCE mode, reset the device by pulling the RESET# signal low. To prevent inadvertent entry into ONCE mode, either configure this pin as an output or hold it high during reset and ensure that your system meets the VIH specification. ONCE# shares a package pin with P2.6. Event Processor Array (EPA) Compare-only Channels with Simulcapture Outputs of the EPA's compare-only channels. These pins are multiplexed with port 9 and may be configured as standard I/O. OS7:0 share package pins with P9.7:0. Port 2 This is a standard, 8-bit, bidirectional port that is multiplexed with individually selectable special-function signals. P2.6 is multiplexed with ONCE#. To prevent inadvertent entry into ONCE mode, either configure this pin as an output or hold it high during reset and ensure that your system meets the VIH specification. Port 2 shares package pins with the following signals: P2.0/TXD0, P2.1/RXD0, P2.2/EXTINT, P2.3/TXD1, P2.4/RXD1, P2.6/ONCE#, and P2.7/CLKOUT. Port 3 This is a memory-mapped, 8-bit, bidirectional port with programmable open-drain or complementary output modes. The pins are shared with the multiplexed address/data bus, which has complementary drivers. P3.7:0 share package pins with AD7:0. Port 4 This is a memory-mapped, 8-bit, bidirectional port with programmable open-drain or complementary output modes. The pins are shared with the multiplexed address/data bus, which has complementary drivers. P4.7:0 share package pins with AD15:8.
NMI
I
ONCE#
I
OS7:0
O
P2.7:0
I/O
P3.7:0
I/O
P4.7:0
I/O
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Table 4. Signal Descriptions (Sheet 5 of 8) Name P5.7:0 Type I/O Description Port 5 This is a memory-mapped, 8-bit, bidirectional port that is multiplexed with individually selectable control signals. P5.4 is multiplexed with TMODE#. If this pin is held low during reset, the device will enter a test mode. To prevent inadvertent entry into a reserved test mode, either configure this pin as an output or hold it high during reset and ensure that your system meets the VIH specification. Port 5 shares package pins with the following signals: P5.0/ALE, P5.1/INST, P5.2/WR#/WRL#, P5.3/RD#, P5.4/BREQ#/TMODE#, P5.5/BHE#/WRH#, P5.6/READY, and P5.7/RPD. Port 7 This is a standard, 8-bit, bidirectional port that is multiplexed with individually selectable special-function signals. Port 7 shares package pins with the following signals: P7.0/EPA0/T1CLK, P7.1/EPA1/T1RST, P7.2/EPA2/T2CLK, P7.3/EPA3/T2RST, P7.4/EPA4/T3CLK, P7.5/EPA5/T3RST, P7.6/EPA6/T4CLK, and P7.7/EPA7/T4RST. Port 8 This is a standard, 8-bit, bidirectional port that is multiplexed with individually selectable special-function signals. P8.7:0 share package pins with EPA15:8. Port 9 This is a standard, 8-bit, bidirectional port that is multiplexed with individually selectable special-function signals. P9.7:0 share package pins with OS7:0. Port 10 This is a standard, 6-bit, bidirectional port that is multiplexed with individually selectable special-function signals. Port 10 shares package pins with the following signals: P10.0/SC0, P10.1/SD0, P10.2/SC1, P10.3/SD1, P10.4/EPA16, and P10.5. Port 11 This is a standard, 8-bit, bidirectional port that is multiplexed with individually selectable special-function signals. P11.7:0 share package pins with PWM7:0. Port 12 This is a memory-mapped, 5-bit, bidirectional port. P12.2:0 select the test-ROM execution mode. Phase-locked Loop Enable This active-high input pin enables the on-chip clock doubler. This pin must be held low when entering on-circuit emulation (ONCE) mode. Pulse Width Modulator Outputs These are PWM output pins with high-current drive capability. PWM7:0 share package pins with P11.7:0.
P7.7:0
I/O
P8.7:0
I/O
P9.7:0
I/O
P10.5:0
I/O
P11.7:0
I/O
P12.4:0
I/O
PLLEN
I
PWM7:0
O
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8xC196EA -- AUTOMOTIVE
Table 4. Signal Descriptions (Sheet 6 of 8) Name RD# Type O Description Read Read-signal output to external memory. RD# is asserted only during external memory reads. RD# shares a package pin with P5.3. Ready Input This active-high input signal is used to lengthen external memory cycles for slow memory by generating wait states in addition to the wait states that are generated internally. When READY is high, CPU operation continues in a normal manner with wait states inserted as programmed in the chip configuration registers or the chip-select x bus control register. READY is ignored for all internal memory accesses. READY shares a package pin with P5.6. Reset A level-sensitive reset input to and open-drain system reset output from the microcontroller. Either a falling edge on RESET# or an internal reset turns on a pull-down transistor connected to the RESET# pin for 16 state times. In the powerdown and idle modes, asserting RESET# causes the chip to reset and return to normal operating mode. After a device reset, the first instruction fetch is from FF2080H (or 1F2080H in external memory). Return from Powerdown Timing pin for the return-from-powerdown circuit. If your application uses powerdown mode, connect a capacitor between RPD and VSS if either of the following conditions are true. * the internal oscillator is the clock source * the phase-locked loop (PLL) circuitry is enabled (see PLLEN signal description) The capacitor causes a delay that enables the oscillator and PLL circuitry to stabilize before the internal CPU and peripheral clocks are enabled. The capacitor is not required if your application uses powerdown mode and if both of the following conditions are true. * an external clock input is the clock source * the phase-locked loop circuitry is disabled If your application does not use powerdown mode, leave this pin unconnected. RPD shares a package pin with P5.7. Receive Serial Data 0 and 1 In modes 1, 2, and 3, RXD0 and 1 receive serial port input data. In mode 0, they functions as either inputs or open-drain outputs for data. RXD0 shares a package pin with P2.1 and RXD1 shares a package pin with P2.4. Clock Pins for SSIO0 and 1 For handshaking mode, configure SC1:0 as open-drain outputs. This pin carries a signal only during receptions and transmissions. When the SSIO port is idle, the pin remains either high (with handshaking) or low (without handshaking). SC0 shares a package pin with P10.0, and SC1 shares a package pin with P10.2.
READY
I
RESET#
I/O
RPD
I
RXD1:0
I/O
SC1:0
I/O
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Table 4. Signal Descriptions (Sheet 7 of 8) Name SD1:0 Type I/O Description Data Pins for SSIO0 and 1 These pins are the data I/O pins for SSIO0 and 1. SD0 shares a package pin with P10.1, and SD1 shares a package pin with P10.1. Timer 1 External Clock External clock for Timer 1.Timer 1 is programmable to increment or decement on the rising edge, the falling edge, or both rising and falling edges of T1CLK. T1CLK shares a package pin with P7.0 and EPA0. Timer 2 External Clock External clock for timer 2. Timer 2 is programmable to increment or decement on the rising edge, the falling edge, or both rising and falling edges of T2CLK. External clock for the serial I/O baud-rate generator input (program selectable). T2CLK shares a package pin with P7.2 and EPA2. Timer 3 External Clock External clock for timer 3. Timer 3 is programmable to increment or decement on the rising edge, the falling edge, or both rising and falling edges of T3CLK. T3CLK shares a package pin with P7.4 and EPA4. Timer 4 External Clock External clock for timer 4. Timer 2 is programmable to increment or decement on the rising edge, the falling edge, or both rising and falling edges of T4CLK. T4CLK shares a package pin with P7.6 and EPA6. Timer 1 External Reset External reset for timer 1. Timer 1 is programmable to reset on the rising edge, the falling edge, or both rising and falling edges of T1RST. T1RST shares a package pin with P7.1 and EPA1. Timer 2 External Reset External reset for timer 2. Timer 2 is programmable to reset on the rising edge, the falling edge, or both rising and falling edges of T2RST. T2RST shares a package pin with P7.3 and EPA3. Timer 3 External Reset External reset for timer 3. Timer 3 is programmable to reset on the rising edge, the falling edge, or both rising and falling edges of T3RST. T3RST shares a package pin with P7.5 and EPA5. Timer 4 External Reset External reset for timer 4. Timer 4 is programmable to reset on the rising edge, the falling edge, or both rising and falling edges of T4RST. T4RST shares a package pin with P7.6 and EPA6. Test-Mode Entry If this pin is held low during reset, the device will enter a test mode. The value of several other pins defines the actual test mode. All test modes, except test-ROM execution, are reserved for Intel factory use. If you choose to configure this signal as an input, always hold it high during reset and ensure that your system meets the VIH specification to prevent inadvertent entry into test mode. TMODE# shares a package pin with P5.4 and BREQ#.
T1CLK
I
T2CLK
I
T3CLK
I
T4CLK
I
T1RST
I
T2RST
I
T3RST
I
T4RST
I
TMODE#
I
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8xC196EA -- AUTOMOTIVE
Table 4. Signal Descriptions (Sheet 8 of 8) Name TXD1:0 Type O Description Transmit Serial Data 0 and 1 In serial I/O modes 1, 2, and 3, TXD0 and 1 transmit serial port output data. In mode 0, they are the serial clock output. TXD0 shares a package pin with P2.0 and TXD1 shares a package pin with P2.3. Digital Supply Voltage Connect each VCC pin to the digital supply voltage. Reference Voltage for the A/D Converter This pin also supplies operating voltage to the analog portion of the A/D converter. Digital Circuit Ground These pins supply ground for the digital circuitry. Connect each VSS pin to ground through the lowest possible impedance path. Write This active-low output indicates that an external write is occurring. This signal is asserted only during external memory writes. WR# is multiplexed with P5.2 and WRL#.
VCC VREF
PWR PWR
VSS
GND
WR#
O
The chip configuration register 0 (CCR0) determines whether this pin functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
WRH#
O
Write High During 16-bit bus cycles, this active-low output signal is asserted for high-byte writes and word writes to external memory. During 8-bit bus cycles, WRH# is asserted for all write operations. WRH# shares a package pin with P5.5 and BHE#.
The chip configuration register 0 (CCR0) determines whether this pin functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
WRL#
O
Write Low During 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes to external memory. During 8-bit bus cycles, WRL# is asserted for all write operations. WRL# shares a package pin with P5.2 and WR#.
The chip configuration register 0 (CCR0) determines whether this pin functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
XTAL1
I
Input Crystal/Resonator or External Clock Input Input to the on-chip oscillator and the internal clock generators. The internal clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When using an external clock source instead of the on-chip oscillator, connect the clock input to XTAL1. The external clock signal must meet the VIH specification for XTAL1. Inverted Output for the Crystal/Resonator Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design uses an external clock source instead of the on-chip oscillator.
XTAL2
O
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5.0
ADDRESS MAP
Table 5. 8xC196EA Address Map (Sheet 1 of 2) Description (Note 1, Note 2) External device (memory or I/O) connected to address/data bus Program memory (Note 3) Program memory (Note 3) Special-purpose memory (PIH vectors; Note 3) Program memory (Note 3); (After reset, the first instruction is fetched from FF2080H.) Special-purpose memory (CCBs, interrupt vectors, PTS vectors; Note 3) External device (memory or I/O) connected to address/data bus Internal code/data RAM (identically mapped from page 00H) Reserved for in-circuit emulators Overlaid memory (reserved for future devices); locations xF0000-xF03FFH are reserved for in-circuit emulators External device (memory or I/O) connected to address/data bus A copy of internal ROM (FF2400-FF3FFFH) if CCB1.2=0 External memory if CCB1.2=1 External device (memory or I/O) connected to address/data bus Memory-mapped special-function registers (SFRs) Addressing Modes Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended -- Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended Indirect, indexed, extended, windowed direct Indirect, indexed, extended Indirect, indexed, extended
Hex Address FFFFFF FF4000 FF3FFF FF2400 FF23FF FF2200 FF21FF FF20C0 FF20BF FF2080 FF207F FF2000 FF1FFF FF1000 FF0FFF FF0400 FF03FF FF0000 FEFFFF 1F0000 1EFFFF 004000 003FFF 002400 0023FF 002000 001FFF 001FE0 001FDF 001C00 001BFF 001000 000FFF 000400
Peripheral special-function registers (SFRs)
External device (memory or I/O) connected to address/data bus Internal code/data RAM (identically mapped into page FFH)
NOTES: 1. Unless otherwise noted, write 0FFH to reserved memory locations and write 0 to reserved SFR bits. 2. The contents or functions of reserved locations may change in future device revisions, in which case a program that relies on one or more of these locations might not function properly. 3. External memory if EA# is low; internal ROM if EA# is high.
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Table 5. 8xC196EA Address Map (Sheet 2 of 2) Hex Address 0003FF 000100 0000FF 00001A 000019 000000 Description (Note 1, Note 2) Upper register file (general-purpose register RAM) Lower register file (general-purpose register RAM) Lower register file (stack pointer and CPU SFRs) Addressing Modes Indirect, indexed, windowed direct Direct, indirect, indexed Direct, indirect, indexed
NOTES: 1. Unless otherwise noted, write 0FFH to reserved memory locations and write 0 to reserved SFR bits. 2. The contents or functions of reserved locations may change in future device revisions, in which case a program that relies on one or more of these locations might not function properly. 3. External memory if EA# is low; internal ROM if EA# is high.
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6.0
ELECTRICAL CHARACTERISTICS
NOTICE: This document contains information on
ABSOLUTE MAXIMUM RATINGS
Storage Temperature .................................. -60C to +150C products in the design phase of development. The Supply Voltage with Respect to VSS ............... -0.5 V to +7.0 V specifications are subject to change without notice. Power Dissipation .......................................................... 1.5 W Verify with your local Intel sales office that you
OPERATING CONDITIONS
have the latest datasheet before finalizing a design.
TC (Case Temperature Under Bias) .............. -40C to +125C VCC (Digital Supply Voltage) .............................. 4.5 V to 5.5 V WARNING: Stressing the device beyond the VREF (Analog Supply Voltage) ........................... 4.5 V to 5.5 V "Absolute Maximum Ratings" may cause permaFXTAL1 (Input frequency for VCC = 4.5 V - 5.5 V) nent damage. These are stress ratings only. Oper(Note 1) ................................................ 20 MHz to 40 MHz
NOTE: 1. This device is static and should operate below 1 Hz, but has been tested only down to 20 MHz.
ation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
6.1
DC Characteristics
Table 6. DC Characteristics at VCC = 4.5 V - 5.5 V (Sheet 1 of 2)
Symbol ICC
Parameter VCC supply current
Min
Typical (Note 1) 120
Max 135
Units mA
Test Conditions XTAL1 = 40 MHz VCC = 5.5 V Device in Reset XTAL1 = 40 MHz VCC = 5.5 V VCC = 5.5 V XTAL1 = 40 MHz VCC = VREF = 5.5 V Device in Reset VCC=5.5 V
IIDLE IPD IREF
Idle mode current Powerdown mode current A/D reference supply current Code RAM VCC Supply Current Maximum injection current per port on bidirectional pins (Note 4) -10
60 50
95
mA A
5
mA
ICRVCC IINJD
110 10
A mA
NOTES: 1. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature with VCC = 5.0 V. 2. For P2.7:0, P3.7:0, P4.7:0, P5.7:0, P6.7:0, P10.3:0, P11.7:0, P12.4:0, AD15:0, EA#, RESET#, PLLEN, NMI, TDI, TCLK, ONCE#, and XTAL1. 3. For P7.7:0, P8.7:0, P9.7:0, and P10.5:4. 4. The maximum injection current is not tested. The device is designed to meet this specification. 5. Pin capacitance is not tested. This value is based on design simulations.
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Table 6. DC Characteristics at VCC = 4.5 V - 5.5 V (Sheet 2 of 2) Symbol ILI Parameter Input leakage current (Standard inputs except analog inputs) Input leakage current (analog inputs) Input high current (NMI only) Input low voltage (Note 2) Input high voltage (Note 2) Input low voltage (Note 3) Input high voltage (Note 3) Output low voltage (output configured as complementary) Output high voltage (output configured as complementary) Output low voltage in reset Output high current in reset -30 -65 -75 -5 -8 -10 VCC - 1 700 10 9 95 VCC - 0.3 VCC - 0.7 VCC - 1.5 0.5 -120 -240 -280 -50 -110 -130 -0.5 0.7 VCC -0.5 0.7 VCC Min -10 Typical (Note 1) Max 10 Units A Test Conditions VSS < VIN < VCC
ILI1 IIH VIL1 VIH1 VIL2 VIH2 VOL1
-300
300 175 0.3 VCC V CC + 0.5 0.4 VCC V CC + 0.5 0.3 0.45 1.5
nA A V V V V V V V V V V V A A A A A A V mV pF k
VSS + 100 mV < VIN < VREF - 100 mV NMI = VCC = 5.5 V
IOL = 200 A IOL = 3.2 mA IOL = 7.0 mA IOH = -200 A IOH = -3.2 mA IOH = -7.0 mA IOL = 15 A VOH2 = VCC - 1.0V V OH2 = VCC - 2.5V V OH2 = VCC - 4.0V V OH3 = VCC - 1.0V V OH3 = VCC - 2.5V V OH3 = VCC - 4.0V IOH = -15 A
VOH1
VOL2 IOH2
IOH3
Output high current in reset on Port 11
VOH2 VHYS CS RRST
Output high voltage in reset Hysteresis voltage on all inputs except XTAL1 Pin Capacitance (any pin to V SS) (Note 5) Pull-up resistor on RESET# pin
VCC = 5.5 V, V IN = 4.0 V
NOTES: 1. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature with VCC = 5.0 V. 2. For P2.7:0, P3.7:0, P4.7:0, P5.7:0, P6.7:0, P10.3:0, P11.7:0, P12.4:0, AD15:0, EA#, RESET#, PLLEN, NMI, TDI, TCLK, ONCE#, and XTAL1. 3. For P7.7:0, P8.7:0, P9.7:0, and P10.5:4. 4. The maximum injection current is not tested. The device is designed to meet this specification. 5. Pin capacitance is not tested. This value is based on design simulations.
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6.2
AC Characteristics -- Multiplexed Bus Mode
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns. Table 7. AC Characteristics, Multiplexed Bus Mode (Sheet 1 of 2) Symbol FXTAL1 f Parameter Frequency on XTAL1, PLL in 1x mode Frequency on XTAL1, PLL in 2x mode Operating frequency, f = FXTAL1; PLL in 1x mode Operating frequency, f = 2FXTAL1; PLL in 2x mode t TAVDV TRLDV TCHDV TRHDZ TRXDX TXHCH TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH Period, t = 1/f Address Valid to Input Data Valid RD# Low to Input Data Valid CLKOUT High to Input Data valid RD# High to Input Data Float Data Hold after RD# Inactive XTAL1 Rising Edge to CLKOUT High or Low CLKOUT Cycle Time CLKOUT High Period CLKOUT Falling to ALE Rising ALE Falling to CLKOUT Rising ALE Cycle Time ALE High Period Address Setup to ALE Low Address Hold after ALE Low ALE Low to RD# Low RD# Low to CLKOUT Low RD# Low to RD# High RD# High to ALE Rising t - 10 t - 15 t - 15 t - 15 - 10 t - 12 t-5 t + 15 10 t - 10 - 10 - 10 4t t + 10 0 3 2t t + 10 10 10 50 Min 20 10 20 25 Max 40 20 40 50 3t - 40 t - 18 2t - 35 t+5 Units MHz (1, 8) MHz (8) MHz (8) ns ns (2) ns (2) ns (9) ns ns ns (9) ns (9) ns (9) ns (9) ns (9) ns (2) ns ns ns ns ns (9) ns (2) ns (3)
NOTES: 1. 20 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz can be applied with an external clock source. 2. If wait states are used, add 2t x n, where n = number of wait states. 3. Assuming back-to-back bus cycles. 4. When forcing wait states using the BUSCON register, add 2t x n. 5. Exceeding the maximum specification causes additional wait states. 6. 8-bit bus only. 7. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed wait state is required. 8. Device is static by design but has been tested only down to 20 MHz. 9. Assumes CLKOUT is operating in divide-by-two mode (f/2).
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8xC196EA -- AUTOMOTIVE
Table 7. AC Characteristics, Multiplexed Bus Mode (Sheet 2 of 2) Symbol TRLAZ TLLWL TQVWH TCHWH TWLWH TWHQX TWHLH TWHBX TWHAX TRHBX TRHAX TWHSH TRHSH TAVYV TCLYX TYLYH Parameter RD# Low to Address Float ALE Low to WR# Low Data Stable to WR# Rising Edge CLKOUT High to WR# Rising Edge WR# Low to WR# High Data Hold after WR# High WR# High to ALE High BHE#, INST Hold after WR# High AD15:8, CSx# Hold after WR# High BHE#, INST Hold after RD# High AD15:8, CSx# Hold after RD# High A20:0, CSx# Hold after WR# High A20:0, CSx# Hold after RD# High AD15:0 Valid to READY Setup READY Hold after CLKOUT Low Non-READY Time 0 t - 12 t - 14 - 10 t - 10 t - 20 t - 15 t-4 t-4 t-5 t-5 0 0 2t - 40 2t - 40 t + 10 10 Min Max 5 Units ns ns
ns (2)
ns (9) ns (2) ns ns ns ns (6) ns ns (6) ns ns ns (4) ns (5, 7, 9) ns
No Upper Limit
NOTES: 1. 20 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz can be applied with an external clock source. 2. If wait states are used, add 2t x n, where n = number of wait states. 3. Assuming back-to-back bus cycles. 4. When forcing wait states using the BUSCON register, add 2t x n. 5. Exceeding the maximum specification causes additional wait states. 6. 8-bit bus only. 7. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed wait state is required. 8. Device is static by design but has been tested only down to 20 MHz. 9. Assumes CLKOUT is operating in divide-by-two mode (f/2).
Table 8. AC Timing Symbol Definitions Signals A B C D
Conditions W X Y WR#, WRH#, WRL# XTAL1 READY H L V X Z High Low Valid No Longer Valid Floating
Address BHE# CLKOUT Input Data
L Q R S
ALE Output Data RD# CSx#
Address bus (demultiplexed mode) or address/data bus (multiplexed mode)
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TCLCL t TCLLH TCHDV TRLCL TCHCL
CLKOUT
TLLCH TLHLH TLLRL TRHLH TLHLL
ALE
TRLRH TRLAZ TRHDZ
RD#
TAVLL TRLDV TLLAX TAVDV Data In TLLWL TWLWH TCHWH TWHLH TWHQX
AD15:0 (read)
Address Out
WR#
TQVWH
AD15:0 (write) BHE#, INST
Address Out
Data Out
Address Out TWHBX, TRHBX
TWHAX, TRHAX
AD15:8 A20:16 CSx#
High Address Out
Extended Address Out TWHSH, TRHSH
A3252-01
Figure 4. System Bus Timing Diagram (Multiplexed Bus Mode)
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8xC196EA -- AUTOMOTIVE
TCLYX (max)
CLKOUT
TAVYV TCLYX (min)
READY
TLHLH + 2t
ALE
TRLRH + 2t
RD# AD15:0 (read) WR#
TRLDV + 2t TAVDV + 2t Address Out TWLWH + 2t Data In
TQVWH + 2t
AD15:0 (write) BHE#, INST A20:16 CSx#
Address Out
Data Out
Extended Address Out
A3249-01
Figure 5. READY Timing Diagram (Multiplexed Bus Mode)
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6.3
AC Characteristics -- Demultiplexed Bus Mode
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns. Table 9. AC Characteristics, Demultiplexed Bus Mode (Sheet 1 of 2) Symbol FXTAL1 f Parameter Frequency on XTAL1, PLL in 1x mode Frequency on XTAL1, PLL in 2x mode Operating frequency, f = FXTAL1; PLL in 1x mode Operating frequency, f = 2FXTAL1; PLL in 2x mode t TAVDV TRLDV TAVWL TAVRL TSLDV TCHDV TRHDZ TRHRL TRXDX TXHCH TCLCL TCHCL TCLLH TRLCL TRLRH TRHLH TWLCL TQVWH Period, t = 1/f Address Valid to Input Data Valid RD# Low to Input Data Valid Address Valid to WR# Low Address Valid to RD# Low Chip Select Low to Data Valid CLKOUT Rising Edge to Input Data Valid RD# High to Input Data Float Read High to Next Read Low Data Hold after RD# Inactive XTAL1 High to CLKOUT High or Low CLKOUT Cycle Time CLKOUT High Period CLKOUT Falling ALE Rising RD# Low to CLKOUT Low RD# Low to RD# High RD# Rising to ALE Rising WR# Low to CLKOUT Falling Data Stable to WR# Rising Edge t-5 0 10 2t t - 10 - 10 -5 3t - 12 t-4 - 12 3t - 18 t + 12 5 t + 10 10 5 35 t t-8 4t - 27 2t - 25 t-5 Min 20 10 20 25 Max 40 20 40 50 4t - 23 3t - 25 Units MHz (1,8) MHz (8) Mhz ns ns (2) ns (2) ns ns ns (2) ns (9) ns ns ns ns (9) ns (9) ns (9) ns (9) ns (9) ns (2)
ns (3)
ns (9) ns (3)
NOTES: 1. 20 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz can be applied with an external clock source. 2. If wait states are used, add 2t x n, where n = number of wait states. 3. Assuming back-to-back bus cycles. 4. When forcing wait states using the BUSCON register, add 2t x n. 5. Exceeding the maximum specification causes additional wait states. 6. 8-bit bus only. 7. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed wait state is required. 8. Device is static by design but has been tested only down to 20 MHz. 9. Assumes CLKOUT is operating in divide-by-two mode (f/2).
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8xC196EA -- AUTOMOTIVE
Table 9. AC Characteristics, Demultiplexed Bus Mode (Sheet 2 of 2) Symbol TCHWH TWLWH TWHQX TWHBX TWHAX TRHBX TRHAX TAVYV TCLYX TYLYH Parameter CLKOUT High to WR# Rising Edge WR# Low to WR# High Data Hold after WR# Rising Edge BHE#, INST Hold after WR# High A20:0, CSx# Hold after WR# High BHE#, INST Hold after RD# High A20:0, CSx# Hold after RD# High A20:0 Valid to READY Setup READY Hold after CLKOUT Low Non READY Time 0 Min -5 3t - 15 t t 0 t 0 3t - 25 2t - 28 t + 15 Max 10 Units ns (9) ns (2) ns ns ns ns ns ns (4) ns (5, 7,9) ns
No Upper Limit
NOTES: 1. 20 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz can be applied with an external clock source. 2. If wait states are used, add 2t x n, where n = number of wait states. 3. Assuming back-to-back bus cycles. 4. When forcing wait states using the BUSCON register, add 2t x n. 5. Exceeding the maximum specification causes additional wait states. 6. 8-bit bus only. 7. The first falling edge of READY is not synchronized to a CLKOUT edge; therefore, one programmed wait state is required. 8. Device is static by design but has been tested only down to 20 MHz. 9. Assumes CLKOUT is operating in divide-by-two mode (f/2).
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ADVANCE INFORMATION
8xC196EA -- AUTOMOTIVE
TCHCL TCLLH
TCLCL
t TCHWH
CLKOUT
TRHLH
ALE
TRHRL TRHDZ TRHAX
TAVRL
TRLRH TCHDV TRLDV TAVDV TSLDV Data In TWLCL
RD#
AD15:0 (read)
TAVWL
TWHQX TWHAX TWLWH
WR#
TQVWH
AD15:0 (write) BHE#, INST A20:0 CSx#
Address Out
Data Out TWHBX, TRHBX
A5397-01
Figure 6. System Bus Timing Diagram (Demultiplexed Bus Mode)
ADVANCE INFORMATION
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8xC196EA -- AUTOMOTIVE
TCHYX (max)
CLKOUT
TAVYV TCHYX (min)
READY
TLHLH + 2t
ALE
TRLRH + 2t
RD#
TRLDV + 2t
AD15:0 (read) WR#
TAVDV + 2t Data In TWLWH + 2t
TQVWH + 2t
AD15:0 (write) BHE#, INST A20:16 CSx#
Data Out
Extended Address Out
A5398-01
Figure 7. READY Timing Diagram (Demultiplexed Bus Mode)
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ADVANCE INFORMATION
8xC196EA -- AUTOMOTIVE
6.4
Deferred Bus Timing Mode
Deferred Bus Cycle Mode: This bus mode (enabled by setting CCB1.5) reduces bus contention when using the 8xC196EA in demultiplexed mode with
slow memories. As shown in Figure 8, a delay of 2t occurs in the first bus cycle following a chip-select output change and the first write cycle following a read cycle.
CLKOUT
TLHLH + 2t TWHLH + 2t
ALE
TRHLH + 2t TAVRL + 2t
RD#
TAVDV+ 2t
AD15:0 (read) WR# AD15:0 (write) BHE#, INST A20:0 CSx#
Data In TAVWL + 2t
Data In
Data Out
Data Out
Data Out
Address Out
Valid
Valid
A3246-02
Figure 8. Deferred Bus Mode Timing Diagram
ADVANCE INFORMATION
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8xC196EA -- AUTOMOTIVE
6.5
AC Characteristics -- Serial Port, Shift Register Mode
Table 10. Serial Port Timing -- Shift Register Mode
Symbol TXLXL
Parameter Serial Port Clock period SP_BAUD x002H SP_BAUD = x001H
Min 6t 4t 4t - 27 2t - 27 4t - 30 2t - 30
Max
Units ns ns ns ns ns ns
TXLXH
Serial Port Clock falling edge to rising edge SP_BAUD x002H SP_BAUD = x001H 4t + 27 2t + 27
TQVXH TXHQX TXHQV TDVXH TXHDX TXHQZ
Output data setup to clock high Output data hold after clock high Next output data valid after clock high Input data setup to clock high Input data hold after clock high Last clock high to output float
2t + 30 2t + 30 0 t + 30
ns ns ns ns
The minimum baud-rate (SP_BAUD) register value for receive is x002H and the minimum baud-rate (SP_BAUD) register value for transmit is x001H.
TXLXL TXDx TQVXH RXDx (Out) RXDx (In)
0 1 2
TXLXH
3
TXHQV
4
TXHQX
5 6
TXHQZ
7
TDVXH
Valid Valid Valid
TXHDX
Valid Valid Valid Valid Valid
A2080-03
Figure 9. Serial Port Waveform -- Shift Register Mode
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8xC196EA -- AUTOMOTIVE
6.6
AC Characteristics -- Synchronous Serial Port
Table 11. Synchronous Serial Port Timing
Symbol TCLCL TCLCH TD1DV TCXDV TCXDX TDVCX TDXCX
Parameter Synchronous Serial Port Clock period Synchronous Serial Port Clock falling edge to rising edge Setup time for MSB output Setup time for D6:0 output Output data hold after clock low Setup time for input data Input data hold after clock high
Min 8t 4t 2t
Max
Units ns ns ns
3t + 20 t 10 t+5 3t + 20
ns ns ns ns
SCx (normal transfers)
1
2
3
4
5
6
7
8
TCLCH TCLCL
STE Bit
SDx (out)
MSB
D6
D5
D4
D3
D2
D1
D0
TD1DV
SDx (in)
valid valid valid valid valid valid valid valid
TDVCX
SCx (handshaking transfers) 1 2 3 4 5 6 7
TDXCX
8
TCXDX
TCXDV
Slave Receiver Pulls SCx low
A4512-01
Figure 10. Synchronous Serial Port
ADVANCE INFORMATION
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8xC196EA -- AUTOMOTIVE
6.7
A/D Sample and Conversion Times
Two parameters, sample time and conversion time, control the time required for an A/D conversion. The sample time is the length of time that the analog input voltage is actually connected to the sample capacitor. If this time is too short, the sample capacitor will not charge completely. If the sample time is too long, the input voltage may change and cause conversion errors. The conversion time is the length of time required to convert the analog input voltage stored on the sample capacitor to a digital value. The conversion time must be long enough for the comparator and circuitry to settle and resolve the voltage. Excessively long conversion times allow the sample capacitor to discharge, degrading accuracy. The AD_TIME register programs the A/D sample and conversion times. Use the TSAM and TCONV specifications in Table 12 and Table 14 to determine appropriate values for SAM and CONV; otherwise, erroneous conversion results may occur. When the SAM and CONV values are known, write them to the AD_TIME register. Do not write to this register while a conversion is in progress; the results are unpredictable. Use the following formulas to determine the SAM and CONV values. TS A M x f - 2 SAM = -----------------------------8 where: SAM CONV TSAM TCONV f B equals a number, 1 to 7 equals a number, 2 to 31 is the sample time, in sec (Table 12 and Table 14) is the conversion time, in sec (Table 12 and Table 14) is the operating frequency, in MHz is the number of bits to be converted (8 or 10) TCO NV x f - 3 CONV = --------------------------------- - 1 2xB
At 40 Mhz, to meet TSAM and TCONV minimum specifications: 10-bit mode:
SAM = [ 5, 6, 7 ] T SAM 1s CONV = [ 18, 19, 20, ..., 31 ] T CONV 10s SAM = [ 5, 6, 7 ] T SAM 1s CONV = [ 23, 24, ..., 31 ] T CONV 10s
8-bit mode:
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8xC196EA -- AUTOMOTIVE
6.7.1
AC CHARACTERISTICS -- A/D CONVERTER, 10-BIT MODE
Table 12. 10-bit A/D Operating Conditions (1) Symbol TC VCC VREF TSAM TCONV Description Case Temperature Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Min - 40 4.50 4.50 1.0 10.0 15.0 Max + 125 5.50 5.50 Units C V V s s 2 3 3 Notes
NOTES: 1. ANGND and VSS should nominally be at the same potential. 2. VREF must not exceed VCC by more than + 0.5 V because VREF supplies both the resistor ladder and the analog portion of the converter and input port pins. 3. Program the AD_TIME register to meet the TSAM and TCONV specifications.
Table 13. 10-bit Mode A/D Characteristics Over Specified Operating Conditions (7) (Sheet 1 of 2) Parameter Resolution Absolute Error Full-scale Error Zero Offset Error Nonlinearity Differential Nonlinearity Channel-to-channel Matching Repeatability Temperature Coefficients: Offset Full-scale Differential Nonlinearity Off-isolation 0.1 0.25 0.009 0.009 0.009 - 60 0.25 0.5 0.25 0.5 1.0 2.0 - 0.75 0 0 3.0 + 0.75 1.0 Typical (2) Min 1024 10 0 Max 1024 10 3.0 Units (1) Levels Bits LSBs LSBs LSBs LSBs LSBs LSBs LSBs LSB/C LSB/C LSB/C dB 2, 3, 4 Notes
NOTES: 1. An LSB, as used here, has a value of approximately 5 mV. 2. Most parts will meet these values at 25C, but they are not tested or guaranteed. 3. DC to 100 KHz. 4. Multiplexer break-before-make guaranteed. 5. Resistance from device pin, through internal multiplexer, to sample capacitor. 6. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted. 7. All conversions were performed with processor in idle mode. 8. 100 mV < V IN < VREF - 100 mV.
ADVANCE INFORMATION
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8xC196EA -- AUTOMOTIVE
Table 13. 10-bit Mode A/D Characteristics Over Specified Operating Conditions (7) (Sheet 2 of 2) Parameter Feedthrough VCC Power Supply Rejection Input Series Resistance Voltage on Analog Input Pin Sampling Capacitor DC Input Leakage 3.0 100 - 300 300 Typical (2) - 60 - 60 750 ANGND 1.2K VREF Min Max Units (1) dB dB
Notes 2, 3 2, 3 5 6
V pF nA
8
NOTES: 1. An LSB, as used here, has a value of approximately 5 mV. 2. Most parts will meet these values at 25C, but they are not tested or guaranteed. 3. DC to 100 KHz. 4. Multiplexer break-before-make guaranteed. 5. Resistance from device pin, through internal multiplexer, to sample capacitor. 6. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted. 7. All conversions were performed with processor in idle mode. 8. 100 mV < VIN < VREF - 100 mV. 6.7.2 AC CHARACTERISTICS -- A/D CONVERTER, 8-BIT MODE Table 14. 8-bit A/D Operating Conditions (1) Symbol TC vCC vREF TSAM TCONV Description Case Temperature Digital Supply Voltage Analog Supply Voltage Sample Time Conversion Time Min - 40 4.50 4.50 1.0 8.0 15.0 Max + 125 5.50 5.50 Units Note s
C
V V s s 2 3 3
NOTES: 1. ANGND and VSS should nominally be at the same potential. 2. VREF must not exceed VCC by more than + 0.5 V because VREF supplies both the resistor ladder and the analog portion of the converter and input port pins. 3. Program the AD_TIME register to meet the TSAM and TCONV specifications.
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8xC196EA -- AUTOMOTIVE
Table 15. 8-bit Mode A/D Characteristics Over Specified Operating Conditions (7) Parameter Resolution Absolute Error Full-scale Error Zero Offset Error Nonlinearity Differential Nonlinearity Channel-to-channel Matching Repeatability Temperature Coefficients: Offset Full-scale Differential Nonlinearity Off Isolation Feedthrough VCC Power Supply Rejection Input Series Resistance Voltage on Analog Input Pin Sampling Capacitor DC Input Leakage 3.0 100 - 300 300 - 60 - 60 750 ANGND 1.2K VREF 0.25 0.003 0.003 0.003 - 60
0.5
Typical (2)
Min 256 8 0
Max 256 8 1.0
Units (1) Levels Bits LSBs LSBs LSBs
Notes
0.5 0 - 0.5 0 0 1.0 + 0.5 1.0
LSBs LSBs LSBs LSBs LSB/C LSB/C LSB/C dB dB dB V pF nA 8 2, 3, 4 2, 3 2, 3 5 6
NOTES: 1. An LSB, as used here, has a value of approximately 20 mV. 2. Most parts will need these values at 25C, but they are not tested or guaranteed. 3. DC to 100 KHz. 4. Multiplexer break-before-make guaranteed. 5. Resistance from device pin, through internal multiplexer, to sample capacitor. 6. Applying voltage beyond these specifications will degrade the accuracy of other channels being converted. 7. All conversions were performed with processor in idle mode. 8. 100 mV < V IN < VREF - 100 mV.
ADVANCE INFORMATION
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8xC196EA -- AUTOMOTIVE
6.8
External Clock Drive
Table 16. External Clock Drive Symbol Parameter Oscillator Frequency (FXTAL1) Oscillator Period (TXTAL1) High Time Low Time Rise Time Fall Time Min 10 25 0.35TXTAL1 0.35TXTAL1 Max 40 (1) 100 0.65TXTAL1 0.65TXTAL1 10 10 Units MHz (2) ns ns ns ns ns
1/TXLXL TXLXL TXHXX TXLXX TXLXH TXHXL
NOTES: 1. 20 MHz is the maximum input frequency when using an external crystal oscillator; however, 40 MHz can be applied with an external clock source. 2. These values represent PLL-bypass mode.
TXHXX 0.7 VCC + 0.5 V XTAL1
TXLXH TXLXX 0.3 VCC - 0.5 V 0.7 VCC + 0.5 V 0.3 VCC - 0.5 V TXLXL
TXHXL
A2119-03
Figure 11. External Clock Drive Waveforms
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ADVANCE INFORMATION
8xC196EA -- AUTOMOTIVE
6.9
Test Output Waveforms
3.5 V
2.0 V Test Points 0.8 V
2.0 V 0.8 V
0.45 V
Note: AC testing inputs are driven at 3.5 V for a logic "1" and 0.45 V for a logic "0". Timing measurements are made at 2.0 V for a logic "1" and 0.8 V for a logic "0".
A2120-04
Figure 12. AC Testing Output Waveforms
VLOAD + 0.15 V VLOAD VLOAD - 0.15 V Timing Reference Points
VOH - 0.15 V
VOL + 0.15 V
Note: For timing purposes, a port pin is no longer floating when a 150 mV change from load voltage occurs and begins to float when a 150 mV change from the loading VOH/VOL level occurs with IOL/IOH 15 mA.
A2121-03
Figure 13. Float Waveforms During 5.0 Volt Testing
ADVANCE INFORMATION
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8xC196EA -- AUTOMOTIVE
7.0
THERMAL CHARACTERISTICS
All thermal impedance data is approximate for static air conditions at 1 W of power dissipation. Values change depending on operating conditions and the application. The Intel Packaging Handbook (order number 240800) describes Intel's thermal impedance test methodology. The Components Quality and Reliability Handbook (order number 210997) provides quality and reliability information. Table 17. Thermal Characteristics Package Type 160-pin QFP JA 34C/W JC 5C/W
7.1
8xC196EA Errata
The 8xC196EA may contain design defects or errors known as errata. Characterized errata that may cause the 8xC196EA's behavior to deviate from published specifications are documented in a specification update. Specification updates can be obtained from your local Intel sales office or from the World Wide Web (www.intel.com).
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ADVANCE INFORMATION
8xC196EA -- AUTOMOTIVE
8.0
DATASHEET REVISION HISTORY
This datasheet is valid for devices with an "C" at the end of the topside field process order (FPO) number. Datasheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices. This is the -003 version of the datasheet. The following changes were made in this version: Table 18. Revision History (rev. 002 - 003) (Sheet 1 of 2) Item Data Sheet Figure 1 on page -1 Table 4 on page -7 Description Added 80C196EA device to heading. All device references changed to 8xC196EA. Revised drawing to reflect "8xC196EA". A15:0 - Type - Changed "I/O" to "O" only. AD15:0 - Description - 8-bit Demultiplexed Mode: Added last paragraph "AD7:0 share package pins P3.7:0. AD15:8 share package pins P4.7:0." CRIN - Description: Changed "byte" to "bit". CROUT - Description: Changed "byte" to "bit". ONCE# - Description - 1st paragraph: Added second sentence "PLLEN must also be held low." PLLEN - Description: Added last paragraph "This pin must be held low when entering on-circuit emulation (ONCE) mode." T1CLK - Description: Removed sentence "External clock for the serial I/O baud-rate generator input (program selectable)." T2CLK - Description: Added sentence "External clock for the serial I/O baud-rate generator input (program selectable)." XTAL1 - Description: Corrected spelling "sourcel" to "source". IPD: * Typical: Changed "20" to "50" * Max: Changed "50" to "blank" IREF - Max: Changed TBD to "5". ICRVCC - Added row. IHO2: * Min: Changed VOH2=VCC-2.5 V to "-65", VOH2=VCC -4.0 V to "-75" * Units: Changed all from "mA" to "A" IHO3: * Parameter: Changed "Port 12"to "Port 11" * Min: Changed VOH3=VCC-1.0 V to "-5", VOH3=VCC-2.5 V to "-8", VOH3=VCC-4.0 V to "-10" * Units: Changed all from "mA" to "A".
Table 6 on page -17
ADVANCE INFORMATION
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8xC196EA -- AUTOMOTIVE
Table 18. Revision History (rev. 002 - 003) (Sheet 2 of 2) Item Table 7 on page -19 Description FXTAL1 - Min: * 1x mode changed from "15" to "20" * 2x mode changed from "8" to "10" f - Min: Changed from "15" to "20". t - Max: Changed from "62.5" to "50". TRLRH - Min: Changed from "t-10" to "t-12". TCHWH - Max: Changed from "5" to "10". TWHQX - Min: Changed from "t-15" to "t-20". Note 1: "16 MHz" changed to "20 MHz". FXTAL1 - Min: * 1x mode changed from "15" to "20" * 2x mode changed from "8" to "10" f - Min: Changed from "15" to "20". t - Max: Changed from "62.5" to "50". TCHCL - Min: Changed from "t-5" to "t-10"; Max: Changed from "t+5" to "t+10". TCLLH - Min: Changed from "-5" to "-10"; Max: Changed from "5" to "10". TRLRH - Min: Changed from "3t-10" to "3t-12". TWLWH - Min: Changed from "3t-12" to "3t-15". TAVYV - Max: Changed from "3t-23" to "3t-25". Note 1: "16 MHz" changed to "20 MHz". TD1DV - Symbol: Changed TD1VD" to "TD1DV". TD1DV - Min: Changed TBD to "2t". Revised figure. DC Input Leakage * Min - Changed "0" to "-300" * Max - Removed "" from "300" Note 2: Changed "need" to "meet". DC Input Leakage: * Typical: Added "" to "100" * Min: Changed "0" to "-300" 1/TXLXL - Min: Changed "8" to "10". TXLXL: * Min: Changed "50" to "25" * Max: Changed "125" to "100" Note 1: * Changed "16 MHz" to "20 MHz" * Changed "32 MHz" to "40 MHz"
Table 9 on page -23
Table 11 on page -29 Figure 10 on page -29 Table 13 on page -31
Table 15 on page -33
Table 16 on page -34
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ADVANCE INFORMATION
8xC196EA -- AUTOMOTIVE
Table 19. Revision History (rev. 001 - 002) Item Data Sheet Cover "DC Characteristics" on page -17 Description Status changed from "Product Preview" to "Advance Information". The frequency designation was changed from 32 MHz to 40 MHz. The following DC characteristics specifications were either changed or added: * * "AC Characteristics -- Multiplexed Bus Mode" on page -19 ICC (max) IIDLE (max) * IOH2 * IOH3
The following AC characteristics multiplexed bus mode specifications were changed: * * * * TCHCL (max) TLLCH (min/max) TRLCL (max) TCHWH (min) * * * * TWHLH (max) TAVYV (max) TCLYX (max) TWHQX (min) * * TLLAX (min) TRLDV (max)
"AC Characteristics -- Demultiplexed Bus Mode" on page -23
The following AC characteristics demultiplexed bus mode specifications were changed: * * * * * * * TAVDV (max) TRLDV (max) TSLDV (max) TCHDV (max) TXHCH min/(max) TCHCL (min/max) TCLLH (min/max) * * * * * * * TRLCL (min) TRLRH (min) TRHLH (max) TWLCL (min) TQVWH (min) TCHWH (min) TWLWH (min) * * * * * TWHQX (max) TWHBX (min) TRHBX (min) TAVYV (max) TCLYX (max)
"AC Characteristics -- Demultiplexed Bus Mode" on page -23
The following AC characteristics demultiplexed bus mode specifications were removed: * * TLLCH TLHLH * TLHLL * TWHLH
Figure 6 on page -25 Figure 5 on page -22 HOLD#/HLDA# Timings Table 11 on page -29 "A/D Sample and Conversion Times" on page -30 Table 15 on page -33
Address out line in the System Bus Timing Diagram (Demultiplexed Bus Mode) was corrected from A20:16 to A20:0. TCHYX (max) timing was corrected in the Ready Timing Diagram to show the rising edge of READY after the falling edge of CLKOUT. Section was removed, and all references to either HOLD# or HLDA# were removed. Synchronous Serial timing specifications changed in table. A/D sample and conversion times example added. Note 1 of the 8-bit mode A/D characteristics table changed to state 20 mV, instead of 5 mV.
ADVANCE INFORMATION
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8xC196EA -- AUTOMOTIVE
Table 20. Revision History (rev. 001) Item Table 17 Description Package thermal characteristics changed.
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